Wednesday, March 27, 2013
SPARC T5 and M5 systems released
The M5 processor is also based on the S3 core (rebranded M4) clocked at 3.6Ghz but is has 6 cores and 48MB L3$. The M systems supports up to 32 M5 processor so a fully configured systems will have 192 cores and 1536 strands (hardware threads). The M5-32 have 32TB of memory in a single system.
Old and existing processors for reference:
T3 16 cores @ 1.65GHz 6Mb L2$ 1-4 socket systems PCIe 2.0
T4 8 cores @ 3.0GHz 4MBL3$ 1-4 socket systems PCIe 2.0
New processors:
T5 16 cores @ 3.6GHz 8MB L3$1-8 socket systems PCIe 3.0
M5 6 cores @ 3.6Ghz 48MB L3$ 32 socket system PCIe 3.0
Oracle claims 2.3x performance gain compared to the T4 with increased single-thread performance.
All new systems both T5 and M5 supports LDOM (Oracle VM for SPARC).
Did everyone read that the M5-32 Supports 32TB of memory? No wounder they had to rewrite the virtual memory subsystem in Solaris 11.1
SPARC Servers
Saturday, February 23, 2013
T5,M4 and Athena support in S10U11
7086173 Solaris support for SPARC M4 platforms 7086179 Solaris support for SPARC T5 platforms
7124696 Solaris support for Athena processor
7142242 Solaris support for Fujitsu's SPARC64-X Athena platforms
The Oracle SPARC T5 and M4 processors are unannounced when I write this but the T5 are expected early 2013.
getupdates.oracle.com/readme/147147-26
Wednesday, February 13, 2013
LDOM 3.0, T5 and M10
"To enable all the OracleVM Server for SPARC 3.0 features, you must run the required
system firmware versions on the following platforms:
UltraSPARC T2 server Run at least version 7.4.2 of the system firmware. UltraSPARC T2 Plus server Run at least version 7.4.2 of the system firmware. SPARC T3 server Run at least version 8.2.1.b of the system firmware. SPARC T4 server Run at least version 8.2.1.b of the system firmware. SPARC T5 server Use any installed version of the system firmware.
This firmware is preinstalled on the SPARC T4 and SPARC T5 servers. The required firmware for Fujitsu M10 systems is preinstalled on your system. For information about the required Oracle Solaris OS version, see “Required and Recommended Oracle Solaris OS Versions” on page 12."
The new SPARC M10 systems can now be seen on Fujitsus site (English translation).
From the Register: Fujitsu launches 'Athena' Sparc64-X servers in Japan
Tuesday, October 9, 2012
SPARC T5, M4 and SPARC64-X
SPARC T5 (early next year)
- 16 Cores 128 threads
- 28nm
- 25% increased thread performance to T4
- 2.5x throughput compared to T4
- Scales from 1 to 8 processors
- PCIe Gen 3
- 8MB L3 cache
- LDOM virtualization (as with all previous T-series)
- Solaris 10 update 11 or Solaris 11.1
- 6 cores 48 threads
- Scales to 32+ sockets
- 48MB L2 cache
- 28nm
- 3.6GHz
- 5-6x performance per socket compared to M-series
- LDOM virtualization
- 32TB+ memory configurations
- Solaris 11 only (but S10 support in LDOM)
- LDOM virtualization
- 16 cores 32 threads
- 24MB L2 Cache
- 3 GHz
- On Chip DB floating point
- Crypto acceleration
- Runs both S10 and S11 in lab
Sunday, August 19, 2012
Solaris 10 10/12 and T5-8
Not much is known about this release more than that it will probably feature a ZFS tech refresh, fully integrate OCM and live upgrade enhancements. It could possibly also support the new T5 processors since they might be quite similar to the current T4 processors except for the doubling of cores.
I have also seen fragments of information indicating that Oracle was running Solaris 11 Update 1 on SPARC T5-8 machines as early as March.
Friday, August 17, 2012
Upcoming SPARC CPUs
"SPARC64 X; Fujitsu’s new generation 16 core processor for the next generation UNIX servers
16-core SPARC T5 CMT Processor with glueless 1-hop scaling to 8-sockets"
The SPARC T5 is expected to be built using 28nm technology and double the number of cores compared to the current T4 processor. The Sun Oracle server line should also include a 8 processor version, T5-8 which will then be have four times the number of cores (128) compared to the current T4-4 (32).
This session will be held August 29, hopefully more information will surface afterwards. Otherwise it would be a safe bet to say that we will know more about the SPARC T5 after Oracle OpenWorld in October.
The Register has an article about both the T5 and the M4: Drilling into Oracle's performance boasts.
Tuesday, May 22, 2012
Solaris 11 / SPARC News
Solaris 11 Update 1 (late this year)
- Updated Virtual memory subsystem This is probably what has been known as vm 2.0 earlier
- Faster Solaris 11 updates with improved python performance
- Already running on the upcoming T5/M4 SPARC(R) chips
- VNIC configuration switch hosts with their zones
- Hotpatching similar to KSplice (Remember DUKS in Solaris 8?)
- Offloading of compression and Oracle arithmetics to CPU besides crypto
- Schedulers for DB or JVM workloads
Wednesday, October 12, 2011
SPARC presentations from OOW
Since there should be few differences between a T4 and T5 besides the 28nm shrink, double the cores and possibly a frequency bump it seems like it could be possible squeeze the time to market for that design. (With few differences I mean that the core itself is ready)
Next Generation SPARC Processor, An In-Depth Technical Review
SPARC Strategy
Monday, December 6, 2010
More SPARC T4/T5 information
"Going forward, the SPARC T4 is less than 12 months away. So that's pretty quick. And there's a reason behind that. We wanted to get more single thread performance into the SPARC T-series systems sooner rather than later. So we developed a new core for the SPARC T4 that brings together the combination of throughput performance through threading as well as really high-speed single thread performance. It's really breakthrough technology for us. Referring back to the timeline for development that we have, we developed that core and that technology back in 2006/2007 and we'll be delivering that to the market in 2011.
And then the SPARC T5 will have 16 cores as opposed to the eight cores that we have in the SPARC T4, in 28 nanometer technology. As we go forward with each of these new introductions we'll make sure that the interfaces that deal with memory are common and are contemporary with the sweet spot of memory technology."
Read the whole article here.